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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MCM69Q536/D
Advance Information
MCM69Q536
32K x 36 Bit Synchronous Separate I/O SRAM
The Motorola MCM69Q536 is a 1 Megabit static random access memory, organized as 32K words of 36 bits. It features separate data input and data output buffers and incorporates input and output registers on board with high speed SRAM. The MCM69Q536 allows the user to perform transparent writes and data pass through. Two data bus ports are provided -- a data input (D) and a data output (Q) port. The synchronous design allows for precise cycle control with the use of an external single clock (K). Address port, data input (D0 - D35), data output (Q0 - Q35), write enable (W), chip enables (E1, E2), and pass-through enable (PT) are registered on the rising edge of clock (K). Any given cycle operates on only one address. However, for any cycle, reads and writes can be intermixed. Thus, one can perform a read, a write, or a combination read/ write during any one cycle. For a combination read/write, the contents of the array are read before the new data is written. By using the pass-through function, the output port Q can be made to reflect either the contents of the array or the data presented to the input port D. For read/write or a read cycle with G low, the Q port will output the contents of the array. However, if PT is asserted, the Q port will instead output the data presented at the D input port. * * * * * * * * * * * * * * Single 3.3 V 5% Power Supply Fast Access Times: 6/8/10 ns Max Sustained Throughput of 2.98 Gigabits/Second Single Clock Operation Address, Data Input, E1, E2, PT, W, and Data Output Registers on Chip 83 MHz Maximum Clock Cycle Time Self Timed Write Separate Data Input and Data Output Pins Pass-Through Feature Asynchronous Output Enable (G) LVTTL Compatible I/O No Dead Cycles Required for Reads after Writes or for Writes after Reads 176 Pin TQFP Package Simultaneous Reads and Writes -- Routers -- Shared Memory
TQ PACKAGE 176 LEAD TQFP CASE 1101-01
Suggested Applications -- ATM -- Ethernet Switches -- Cell/Frame Buffers -- SNA Switches Product Family Configurations
Part Number Dual Address
MCM69D536 MCM69D618 MCM69Q536 MCM69Q618 MCM67Q709 MCM67Q909
n n
Single Address
Dual I/O
Note 1 Note 1
n n n n
n n
Separate I/O
Note 2 Note 2
n n n n
NOTES: 1. Tie AX and AY address ports together for the part to function as a single address part. 2. Tie GX high for DQX to be inputs and tie WY high and GY low for DQY to be outputs.
This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 3 11/20/97
(c) Motorola, Inc. 1997 MOTOROLA FAST SRAM
MCM69Q536 1
BLOCK DIAGRAM
K
A0 - A14
15
ADDRESS REGISTER
32K x 36 ARRAY
W
WRITE REGISTER
WRITE DRIVER
SENSE AMP
PT
PT REGISTER
PASS-THROUGH
DATA INPUT REGISTER
DATA OUTPUT REGISTER
E1 E2 G
ENABLE REGISTER 1
ENABLE REGISTER 2
D0 - D35
Q0 - Q35
MCM69Q536 2
MOTOROLA FAST SRAM
PIN ASSIGNMENT
VSS Q19 D19 VSS VDD Q18 D18 A6 NC A7 NC VSS NC NC NC NC NC NC NC NC K VDD VSS NC G E2 E1 NC W NC PT A8 NC A9 NC NC NC D17 Q17 VDD VSS D16 Q16 VSS VSS D20 Q20 VDD VSS D21 Q21 D22 Q22 VDD VSS D23 Q23 D24 Q24 VDD VSS D25 Q25 D26 Q26 VDD VSS Q27 D27 Q28 D28 VDD VSS Q29 D29 Q30 D30 VDD VSS Q31 D31 Q32 D32 VDD VSS Q33 D33 VSS 132 1 131 2 130 3 129 4 128 5 127 6 126 7 125 8 124 9 123 10 122 11 121 12 120 13 119 14 118 15 117 16 116 17 115 18 114 19 113 20 112 21 111 22 23 110 109 24 108 25 107 26 106 27 105 28 104 29 103 30 102 31 101 32 100 33 99 34 98 35 97 36 96 37 95 38 94 39 93 40 92 41 91 42 90 43 89 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 VSS Q34 D34 VSS VDD Q35 D35 VSS VSS NC A5 NC A4 NC A3 NC A2 NC A1 NC A0 VSS VDD A10 NC A11 NC A12 NC A13 NC A14 NC NC NC NC NC D0 Q0 VDD V SS D1 Q1 VSS 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 VSS D15 Q15 VSS VDD D14 Q14 D13 Q13 VSS VDD D12 Q12 D11 Q11 VSS VDD D10 Q10 D9 Q9 VSS VDD Q8 D8 Q7 D7 VSS VDD Q6 D6 Q5 D5 VSS VDD Q4 D4 Q3 D3 VSS VDD Q2 D2 VSS
MOTOROLA FAST SRAM
MCM69Q536 3
PIN DESCRIPTIONS
Pin Locations 55, 57, 59, 61, 63, 65, 68, 70, 72, 74, 76, 143, 145, 167, 169 2, 6, 8, 12, 14, 18, 20, 25, 27, 31, 33, 37, 39, 43, 47, 51, 82, 86, 90, 94, 96, 100, 102, 106, 108, 113. 115, 119, 121, 125, 127, 131, 135, 139, 170, 174 150 151 152 Symbol A0 - A14 D0 - D35 Type Input Input Description Synchronous Address Inputs: These inputs are registered and must meet setup and hold times. Synchronous Data Input.
E1 E2 G
Input Input Input
Synchronous Chip Enable: Active low for depth expansion. Synchronous Chip Enable: Active high for depth expansion. Asynchronous Output Enable Input: Low -- enables output buffers (Qx pins). High -- Qx pins are high impedance. Clock: This signal registers the address, data in, and all control signals except G. Pass-through enable: Synchronous. Synchronous Data Output.
156 146 3, 7, 9, 13, 15, 19, 21, 24, 26, 30, 32, 36, 38, 42, 46, 50, 83, 87, 91, 95, 97, 101, 103, 107, 109, 112, 114, 118, 120, 124, 126, 130, 143, 138, 171, 175 148 4, 10, 16, 22, 28, 34, 40, 49, 67, 84, 98, 104, 110, 116, 122, 128, 137, 155, 172 1, 5, 11, 17, 23, 29, 35, 41, 44, 45, 48, 52, 53, 66, 85, 88, 89, 93, 99, 105, 111, 117, 123. 129, 132, 133, 136, 154, 165, 173, 176 54, 56, 58, 60, 62, 64, 69, 71, 73, 75, 77 - 81, 140, 141, 142, 144, 147, 149, 153, 157 - 164, 166, 168
K PT Q0 - Q35
Input Input Output
W VDD VSS
Input Supply Supply
Synchronous Write. + 3.3 V Power Supply. Ground.
NC
--
No Connection: There is no connection to the chip.
TRUTH TABLE
Input at tn Clock Operation O i Write and Pass-Through Write/Read Pass-Through Read Deselected Deselected E1 L L L L X H E2 H H H H L X W L L H H X X PT L H L H X X Data Input D D written to A D written to A D data Don't Care Don't Care Don't Care Result from tn + 1 Clock Data Output Q D data appears Q out from A D data appears Q out from A Q is high-Z Q is high-Z 1 2 3 4 5 6 Notes
NOTES: 1. Write D to array and output D at Q. 2. Output contents of array to Q then write D to array. 3. Output D at Q. Do not write. 4. Output contents of array to Q. Do not write. 5. No operation. 6. No operation.
MCM69Q536 4
MOTOROLA FAST SRAM
tn K
tn + 1
ADDRESS & CONTROL
VALID PIPELINED READ ACCESS
DATA INPUT D
VALID PASS-THROUGH
DATA OUTPUT Q
VALID
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Power Supply Voltage Voltage Relative to VSS for Any Pin Except VDD Output Current Power Dissipation Temperature Under Bias Operating Temperature Storage Temperature -- Plastic Symbol VDD Vin, Vout Iout PD Tbias TA Tstg Value - 0.5 to + 4.6 - 0.5 to VDD + 0.5 20 TBD - 10 to + 85 0 to + 70 - 55 to + 125 Unit V V mA W C C C This is a synchronous device. All synchronous inputs must meet specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits.
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (See Note 1)
Rating Junction to Ambient (@ 200 lfm) Junction to Board (Bottom) Junction to Case (Top) Single Layer Board Four Layer Board Symbol RJA RJB RJC TQFP 40 35 23 9 Unit C/W C/W C/W Notes 2 3 4
NOTES: 1. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, board population, and board thermal resistance. 2. Per SEMI G38-87. 3. Indicates the average thermal resistance between the die and the printed circuit board. 4. Indicates the average thermal resistance between the die and the case top surface via the cold plate method (MIL SPEC-883 Method 1012.1).
MOTOROLA FAST SRAM
MCM69Q536 5
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 5%, TA = 0 to + 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS AND SUPPLY CURRENTS
Parameter Supply Voltage (Operating Voltage Range) Input High Voltage Input Low Voltage Input Leakage Current (All Inputs, Vin = 0 to VDD) Output Leakage Current (E = VIH, Vout = 0 to VDD) AC Supply Current (Iout = 0 mA) (VDD = max, f = fmax) MCM69Q536-6 ns MCM69Q536-8 ns MCM69Q536-10 ns MCM69Q536-6 ns MCM69Q536-8 ns MCM69Q536-10 ns Symbol VDD VIH VIL Ilkg(I) Ilkg(O) IDDA Min 3.135 2.0 - 0.5* -- -- -- -- -- -- -- -- -- 2.4 Max 3.465 VDD + 0.5** 0.8 1.0 1.0 TBD TBD TBD TBD TBD TBD 0.4 VDD Unit V V V A A mA
CMOS Standby Supply Current (Deselected, Clock (K) Cycle Time tKHKH, All Inputs Toggling at CMOS Levels Vin VSS + 0.2 V or VDD - 0.2 V) Output Low Voltage (IOL = + 8.0 mA) Output High Voltage (IOH = - 4.0 mA) * VIL -1.5 V for t tKHKH/2. ** VIH VDD + 1.0 V for t tKHKH/2.
ISB1
mA
VOL VOH
V V
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to + 70C, Periodically Sampled Rather Than 100% Tested)
Parameter Address and Data Input Capacitance Control Pin Input Capacitance Output Capacitance Symbol Cin Cin Cout Max 6 6 8 Unit pF pF pF
MCM69Q536 6
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V 5%, TA = 0 to + 70C, Unless Otherwise Noted)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns Output Timing Reference Level . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 V Output Load . . . . . . . . . . . . . . . . . . Figure 1 Unless Otherwise Noted
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
MCM69Q536-6 Parameter P Cycle Time Clock Access Time Clock Low Pulse Width Clock High Pulse Width Clock High to Data Output Invalid Clock High to Data Output High-Z Output Enable to Output Valid Output Enable to Output Active Output Disable to Output High-Z Setup Times: A0 - A15 W PT E1, E2 D0 - D17 A0 - A15 W PT E1, E2 D0 - D17 Symbol S bl tKHKH tKHQV tKLKH tKHKL tKHQX tKHQZ tGLQV tGLQX tGHQZ tAVKH tWVKH tPTVKH tEVKH tDVKH tKHAX tKHWX tKHPTX tKHEX tKHDX Min 12 -- 4 4 0 -- -- 0 -- 2.5 Max -- 6 -- -- -- 5 6 -- 5 -- MCM69Q536-8 Min 15 -- 6 6 0 -- -- 0 -- 3 Max -- 8 -- -- -- 6 8 -- 6 -- MCM69Q536-10 Min 20 -- 8 8 0 -- -- 0 -- 3 Max -- 10 -- -- -- 7 10 -- 7 -- Unit ns ns ns ns ns ns ns ns ns ns 4 4 3 4 Notes 1 2
Hold Times:
0.5
--
2
--
2
--
ns
3
NOTES: 1. All read and write cycles are referenced from K. 2. Valid data from Clock High will be the data stored at the address or the last valid read cycle. 3. This is a synchronous device. All synchronous inputs must meet the specified setup and hold times with stable logic levels for ALL rising edges of clock (K) while the device is selected. 4. This parameter is sampled and not 100% tested. RL = 50 OUTPUT Z0 = 50 VL = 1.5 V
Figure 1. AC Test Load
MOTOROLA FAST SRAM
MCM69Q536 7
READ CYCLE TIMING
tKHKH K tAVKH A0 - A14 A B tEVKH tKHEX E C D E F G H tKLKH tKHKL
G tGLQV tGLQX Q Q(A) Q(B) Q(C) tKHQZ tKHQV tKHQX Q(E) tGHQZ Q(F)
E low = E1 low, E2 high. E high = E1 high or E2 low.
MCM69Q536 8
MOTOROLA FAST SRAM
COMBINATION READ/WRITE CYCLE TIMING
tKHKH K tKLKH tKHKL
tKHAX A0 - A14 A B C D E F G H
E
G
Q tWVKH W
Q[A]
Q[B]
Q[C] tKHWX
Q(D)
Q(E)
D(F)
tPTVKH
tKHPTX
PT tDVKH D D(B) D(D) tKHDX D(E) D(F) D(G)
NOTES: 1. E low = E1 low and E2 high. E high = E1 high or E2 low. 2. Q[A] = Previous contents of array at address A. 3. Q(A) = Data presented at input port.
MOTOROLA FAST SRAM
MCM69Q536 9
E CONTROLLED WRITE
K
A0 - A14
A
B
C
D
E
F
G
H
W
E
D
D(A)
D(B)
D(C)
D(D)
D(E)
D(F)
D(G)
D(H)
NOTES: 1. E low = E1 low, E2 high. E high = E1 high or E2 low. 2. Only D(B) and D(D) are written to the array.
ORDERING INFORMATION
(Order by Full Part Number) MCM 69Q536 XX
Motorola Memory Prefix Part Number
XX
X
Shipping Method (R = Tape and Reel, Blank = Rails) Speed (6 = 6 ns, 8 = 8 ns, 10 = 10 ns) Package (TQ = TQFP)
Full Part Numbers -- MCM69Q536TQ6 MCM69Q536TQ8 MCM69Q536TQ10 MCM69Q536TQ6R MCM69Q536TQ8R MCM69Q536TQ10R
MCM69Q536 10
MOTOROLA FAST SRAM
PACKAGE DIMENSIONS
TQFP PACKAGE 176 LEAD CASE 1101-01
4X PIN 1 IDENT 1
G P
0.20 H L-M N C L
176
4X 44 TIPS
0.20 T L-M N C L AB AB
132
133
-X- X=L, M, N VIEW Y
3X
VIEW Y -M- B
PLATING
F
BASE METAL
C L -L- B1 V1
V U
0.08
44 45 88 89
ROTATED 90_ CLOCKWISE
SECTION AB-AB
-N- A1 S1 A S
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M-, AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INLCUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.35 (0.014) MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD 0.07 (0.003). MILLIMETERS MIN MAX 24.00 BSC 12.00 BSC 24.00 BSC 12.00 BSC --- 1.60 0.05 --- 1.35 1.45 0.17 0.23 0.45 0.75 0.17 0.27 0.50 BSC 0.09 0.20 0.50 REF 0.25 BSC 0.10 0.20 26.00 BSC 13.00 BSC 0.09 0.16 26.00 BSC 13.00 BSC 0.20 REF 1,00 REF 0_ 7_ 0_ --- 12 _REF
VIEW AA C -H- -T-
SEATING PLANE 4X
q2
0.08 T
0.05 W
S
q1
C2
2X R R1
0.25
GAGE PLANE
C1
K E Z VIEW AA
q
DIM A A1 B B1 C C1 C2 D E F G J K P R1 S S1 U V V1 W Z
q q1 q2
MOTOROLA FAST SRAM
EEEE EEEE CCC EEEE CCC EEEE
D
M
J
T L-M
S
N
S
MCM69Q536 11
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; P.O. Box 5405, Denver, Colorado, 80217. 1-303-675-2140 or 1-800-441-2447 JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 141, 4-32-1 Nishi-Gotanda, Shagawa-ku, Tokyo, Japan. 03-5487-8488
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MCM69Q536 12
MCM69Q536/D MOTOROLA FAST SRAM

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